diff --git a/Wiring/Autorouter_PCB_VL53L7CX-PCB_2_2025-02-07.dsn b/Wiring/Autorouter_PCB_VL53L7CX-PCB_2_2025-02-07.dsn
new file mode 100644
index 0000000000000000000000000000000000000000..1c58a340d63ef40907cdb39256ce53f73a849d16
--- /dev/null
+++ b/Wiring/Autorouter_PCB_VL53L7CX-PCB_2_2025-02-07.dsn
@@ -0,0 +1,829 @@
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+ (wire(path 1 1 21.0826 -30.9256 24.0356 -30.9256 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 29.9409 -35.0591 28.1709 -35.0591 26.1209 -33.0191 24.9009 -33.0191 24.0309 -31.9691 24.0309 -30.9291 )
+ (net GND)
+ (type protect)
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+ (net R3_1)
+ (type protect)
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+ (wire(path 1 1 34.4409 -20.0101 35.8466 -21.4158 35.8466 -30.9256 )
+ (net U2_C2)
+ (type protect)
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+ (wire(path 1 1 35.9409 -35.0591 29.9406 -35.0586 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 35.8509 -39.1891 35.9409 -35.0591 37.9409 -35.0591 37.9409 -31.7891 38.8009 -30.9291 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 41.0209 -20.5591 41.0209 -34.4113 40.3736 -35.0586 )
+ (net VDD)
+ (type protect)
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+ (wire(path 1 1 34.4409 -18.1091 41.0209 -18.1391 41.0209 -20.5591 )
+ (net VDD)
+ (type protect)
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+ (wire(path 1 1 30.4409 -18.1081 34.4409 -18.1081 )
+ (net VDD)
+ (type protect)
+ )
+ (wire(path 1 1 26.4409 -18.1081 30.4409 -18.1081 )
+ (net VDD)
+ (type protect)
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+ (wire(path 1 1 27.3609 -7.5591 27.3609 -17.1882 26.4409 -18.1082 )
+ (net VDD)
+ (type protect)
+ )
+ (wire(path 1 1 31.9409 -10.5591 29.521 -8.1392 29.521 -7.5591 )
+ (net GND)
+ (type protect)
+ )
+ (wire(path 1 1 19.1809 -13.8902 19.4409 -13.6301 19.4409 -10.0591 23.4409 -10.0591 )
+ (net GND)
+ (type protect)
+ )
+ (wire(path 1 1 11.7009 -5.228 14.8699 -2.0591 21.4409 -2.0591 27.3609 -2.0591 )
+ (net VDD)
+ (type protect)
+ )
+ (wire(path 1 1 27.3609 -2.0591 27.3609 -7.559 27.3608 -7.5591 )
+ (net VDD)
+ (type protect)
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+ (wire(path 1 1 19.9409 -20.0591 19.9409 -14.6501 19.1809 -13.8901 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 15.3608 -20.0591 12.9409 -20.0591 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 11.7009 -13.8901 10.5319 -15.0591 4.4409 -15.0591 )
+ (net VIN)
+ (type protect)
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+ (wire(path 1 1 15.4409 -13.8901 11.7009 -13.8901 )
+ (net VIN)
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+ (wire(path 1 1 17.5209 -20.0591 17.4409 -17.0591 15.4409 -17.0591 15.4409 -13.8901 )
+ (net VIN)
+ (type protect)
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+ (wire(path 1 1 17.5209 -24.0591 17.5209 -20.0592 17.521 -20.0591 )
+ (net VIN)
+ (type protect)
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+ (wire(path 1 1 15.3609 -24.0591 14.3609 -25.0591 4.4409 -25.0591 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 15.3608 -24.0591 12.9409 -21.6392 12.9409 -20.0591 )
+ (net GND)
+ (type protect)
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+ (wire(path 1 1 29.9409 -27.5591 26.4409 -24.0591 26.4409 -20.0101 )
+ (net R4_1)
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+ (net R4_1)
+ (type protect)
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+ (wire(path 1 1 12.8909 -32.1091 17.5209 -27.4791 17.5209 -24.0591 )
+ (net VIN)
+ (type protect)
+ )
+ (wire(path 1 1 10.8819 -52.3661 4.4409 -45.9251 4.4409 -45.0591 )
+ (net SCL)
+ (type protect)
+ )
+ (wire(path 1 1 10.4409 -40.0101 5.3919 -45.0591 4.4409 -45.0591 )
+ (net SCL)
+ (type protect)
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+ (wire(path 2 1 40.9409 -44.5591 36.9409 -40.5591 36.9409 -30.5591 34.9409 -28.5591 34.9409 -8.5591 33.4409 -7.0591 10.9409 -7.0591 10.4409 -7.5591 10.4409 -35.5591 )
+ (net SDA)
+ (type protect)
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+ (net GND)
+ (type protect)
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+ (wire(path 2 1 4.9409 -50.0591 12.4409 -50.0591 15.9409 -53.5591 16.4409 -54.0591 39.9409 -54.0591 )
+ (net SCL)
+ (type protect)
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+ (wire(path 2 1 20.4409 -50.0591 20.9409 -49.5591 28.9409 -49.5591 )
+ (net R6_1)
+ (type protect)
+ )
+ (wire(path 2 1 10.4409 -57.5591 26.9409 -57.5591 )
+ (net LPN)
+ (type protect)
+ )
+ (wire(path 2 1 21.2715 -42.0591 21.2715 -23.5591 23.4409 -21.3897 23.4409 -18.0591 )
+ (net VDD)
+ (type protect)
+ )
+ (wire(path 2 1 15.9409 -49.5591 17.4409 -49.5591 21.4409 -45.5591 34.4409 -45.5591 34.9409 -45.0591 34.9409 -31.0591 29.4409 -25.5591 29.4409 -23.0591 )
+ (net R3_1)
+ (type protect)
+ )
+ (wire(path 2 1 18.9409 -32.0591 14.4409 -27.5591 )
+ (net GND)
+ (type protect)
+ )
+ (wire(path 2 1 15.4409 -10.0591 19.4409 -14.0591 29.4409 -14.0591 )
+ (net VIN)
+ (type protect)
+ )
+ (wire(path 2 1 17.4409 -46.0591 16.4409 -46.0591 13.9409 -43.5591 13.9409 -36.5591 12.9409 -35.5591 10.4409 -35.5591 )
+ (net SDA)
+ (type protect)
+ )
+ (wire(path 2 1 32.4409 -43.0591 31.4409 -42.0591 16.4409 -42.0591 )
+ (net VDD)
+ (type protect)
+ )
+ (wire(path 2 1 23.4409 -10.0591 23.9409 -10.5591 31.9409 -10.5591 )
+ (net GND)
+ (type protect)
+ )
+ (wire(path 2 1 12.9409 -20.0591 19.9409 -20.0591 )
+ (net GND)
+ (type protect)
+ )
+ (via via1 12.9409 -20.0591
+ (net GND)
+ (type protect)
+ )
+ (via via1 19.9409 -20.0591
+ (net GND)
+ (type protect)
+ )
+ (via via1 23.4409 -10.0591
+ (net GND)
+ (type protect)
+ )
+ (via via1 31.9409 -10.5591
+ (net GND)
+ (type protect)
+ )
+ (via via1 32.4409 -43.0591
+ (net VDD)
+ (type protect)
+ )
+ (via via1 16.4409 -42.0591
+ (net VDD)
+ (type protect)
+ )
+ (via via1 17.4409 -46.0591
+ (net SDA)
+ (type protect)
+ )
+ (via via1 10.4409 -35.5591
+ (net SDA)
+ (type protect)
+ )
+ (via via1 15.4409 -10.0591
+ (net VIN)
+ (type protect)
+ )
+ (via via1 29.4409 -14.0591
+ (net VIN)
+ (type protect)
+ )
+ (via via1 18.9409 -32.0591
+ (net GND)
+ (type protect)
+ )
+ (via via1 14.4409 -27.5591
+ (net GND)
+ (type protect)
+ )
+ (via via1 15.9409 -49.5591
+ (net R3_1)
+ (type protect)
+ )
+ (via via1 29.4409 -23.0591
+ (net R3_1)
+ (type protect)
+ )
+ (via via1 23.4409 -18.0591
+ (net VDD)
+ (type protect)
+ )
+ (via via1 10.4409 -57.5591
+ (net LPN)
+ (type protect)
+ )
+ (via via1 26.9409 -57.5591
+ (net LPN)
+ (type protect)
+ )
+ (via via1 20.4409 -50.0591
+ (net R6_1)
+ (type protect)
+ )
+ (via via1 28.9409 -49.5591
+ (net R6_1)
+ (type protect)
+ )
+ (via via1 4.9409 -50.0591
+ (net SCL)
+ (type protect)
+ )
+ (via via1 39.9409 -54.0591
+ (net SCL)
+ (type protect)
+ )
+ (via via1 40.9409 -44.5591
+ (net SDA)
+ (type protect)
+ )
+ (via via1 38.4409 -24.5591
+ (net GND)
+ (type protect)
+ )
+ (via via1 45.9409 -30.0591
+ (net GND)
+ (type protect)
+ )
+ )
+
+)
\ No newline at end of file
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new file mode 100644
index 0000000000000000000000000000000000000000..4eede274b6a186915d39f3406272c871ccabcfdc
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diff --git a/Wiring/PCB_PCB_VL53L7CX-PCB_2_2025-02-07.json b/Wiring/PCB_PCB_VL53L7CX-PCB_2_2025-02-07.json
new file mode 100644
index 0000000000000000000000000000000000000000..02be7e66a563ec256217df5fa1b86a1cb7695b1a
--- /dev/null
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@@ -0,0 +1,250 @@
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+ "VIA~4086.972~3411.5~2.441~GND~0.6102~gge6872~0",
+ "VIA~4092~3415.5~2.441~GND~0.6102~gge6879~0"
+ ],
+ "layers": [
+ "1~TopLayer~#FF0000~true~true~true~",
+ "2~BottomLayer~#0000FF~true~false~true~",
+ "3~TopSilkLayer~#FFCC00~false~false~true~",
+ "4~BottomSilkLayer~#66CC33~true~false~true~",
+ "5~TopPasteMaskLayer~#808080~true~false~true~",
+ "6~BottomPasteMaskLayer~#800000~true~false~true~",
+ "7~TopSolderMaskLayer~#800080~true~false~true~0.3",
+ "8~BottomSolderMaskLayer~#AA00FF~true~false~true~0.3",
+ "9~Ratlines~#6464FF~true~false~true~",
+ "10~BoardOutLine~#FF00FF~true~false~true~",
+ "11~Multi-Layer~#C0C0C0~true~false~true~",
+ "12~Document~#FFFFFF~true~false~true~",
+ "13~TopAssembly~#33CC99~false~false~false~",
+ "14~BottomAssembly~#5555FF~false~false~false~",
+ "15~Mechanical~#F022F0~false~false~false~",
+ "19~3DModel~#66CCFF~false~false~false~",
+ "21~Inner1~#999966~false~false~false~~",
+ "22~Inner2~#008000~false~false~false~~",
+ "23~Inner3~#00FF00~false~false~false~~",
+ "24~Inner4~#BC8E00~false~false~false~~",
+ "25~Inner5~#70DBFA~false~false~false~~",
+ "26~Inner6~#00CC66~false~false~false~~",
+ "27~Inner7~#9966FF~false~false~false~~",
+ "28~Inner8~#800080~false~false~false~~",
+ "29~Inner9~#008080~false~false~false~~",
+ "30~Inner10~#15935F~false~false~false~~",
+ "31~Inner11~#000080~false~false~false~~",
+ "32~Inner12~#00B400~false~false~false~~",
+ "33~Inner13~#2E4756~false~false~false~~",
+ "34~Inner14~#99842F~false~false~false~~",
+ "35~Inner15~#FFFFAA~false~false~false~~",
+ "36~Inner16~#99842F~false~false~false~~",
+ "37~Inner17~#2E4756~false~false~false~~",
+ "38~Inner18~#3535FF~false~false~false~~",
+ "39~Inner19~#8000BC~false~false~false~~",
+ "40~Inner20~#43AE5F~false~false~false~~",
+ "41~Inner21~#C3ECCE~false~false~false~~",
+ "42~Inner22~#728978~false~false~false~~",
+ "43~Inner23~#39503F~false~false~false~~",
+ "44~Inner24~#0C715D~false~false~false~~",
+ "45~Inner25~#5A8A80~false~false~false~~",
+ "46~Inner26~#2B937E~false~false~false~~",
+ "47~Inner27~#23999D~false~false~false~~",
+ "48~Inner28~#45B4E3~false~false~false~~",
+ "49~Inner29~#215DA1~false~false~false~~",
+ "50~Inner30~#4564D7~false~false~false~~",
+ "51~Inner31~#6969E9~false~false~false~~",
+ "52~Inner32~#9069E9~false~false~false~~",
+ "99~ComponentShapeLayer~#00CCCC~false~false~false~0.4",
+ "100~LeadShapeLayer~#CC9999~false~false~false~",
+ "101~ComponentMarkingLayer~#66FFCC~false~false~false~",
+ "Hole~Hole~#222222~false~false~true~",
+ "DRCError~DRCError~#FAD609~false~false~true~"
+ ],
+ "objects": [
+ "All~true~false",
+ "Component~true~true",
+ "Prefix~true~true",
+ "Name~true~false",
+ "Track~true~true",
+ "Pad~true~true",
+ "Via~true~true",
+ "Hole~true~true",
+ "Copper_Area~true~true",
+ "Circle~true~true",
+ "Arc~true~true",
+ "Solid_Region~true~true",
+ "Text~true~true",
+ "Image~true~true",
+ "Rect~true~true",
+ "Dimension~true~true",
+ "Protractor~true~true"
+ ],
+ "BBox": {
+ "x": 4047.6,
+ "y": 3385.4,
+ "width": 50,
+ "height": 70
+ },
+ "preference": {
+ "hideFootprints": "",
+ "hideNets": ""
+ },
+ "DRCRULE": {
+ "Default": {
+ "trackWidth": 1,
+ "clearance": 0.5984,
+ "viaHoleDiameter": 2.4016,
+ "viaHoleD": 1.2008
+ },
+ "isRealtime": true,
+ "isDrcOnRoutingOrPlaceVia": false,
+ "checkObjectToCopperarea": true,
+ "showDRCRangeLine": true
+ },
+ "netColors": {}
+}
\ No newline at end of file
diff --git a/Wiring/SCH_VL53L7CX-PCB_2025-02-07.json b/Wiring/SCH_VL53L7CX-PCB_2025-02-07.json
new file mode 100644
index 0000000000000000000000000000000000000000..c8e95f1f6cea92d5d35574e5e5994c07f6df74c7
--- /dev/null
+++ b/Wiring/SCH_VL53L7CX-PCB_2025-02-07.json
@@ -0,0 +1,193 @@
+{
+ "editorVersion": "6.5.46",
+ "docType": "5",
+ "title": "VL53L7CX PCB",
+ "description": "",
+ "colors": {},
+ "schematics": [
+ {
+ "docType": "1",
+ "title": "Sheet_1",
+ "description": "",
+ "dataStr": {
+ "head": {
+ "docType": "1",
+ "editorVersion": "6.5.46",
+ "newgId": true,
+ "c_para": {
+ "Prefix Start": "1"
+ },
+ "c_spiceCmd": "null",
+ "hasIdFlag": true,
+ "uuid": "cefc03a0b05941e2abbb2cb823da25b9",
+ "x": "0",
+ "y": "0",
+ "portOfADImportHack": "",
+ "importFlag": 0,
+ "transformList": ""
+ },
+ "canvas": "CA~1000~1000~#FFFFFF~yes~#CCCCCC~5~1000~1000~line~5~pixel~5~0~0",
+ "shape": [
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